1. Field of the Invention
The present invention relates to a semiconductor memory system having a plurality of semiconductor memory devices and a controller for controlling the read and write operation of each semiconductor memory device which are built in.
2. Description of the Related Art
Referring to FIG. 22, one example for a conventional semiconductor memory system will be explained. FIG. 22 is a block diagram schematically showing an arrangement of the conventional semiconductor memory system having a plurality of semiconductor memory devices of which the data read and write operations are controlled by an external CPU. The semiconductor memory system denoted by 90 includes a couple of first and second semiconductor memory devices 91 and 92 which are different from each other in the way for controlling the data read and write operations. The data read and write operations of the semiconductor memory devices 91 and 92 are controlled using commands from an external CPU 99.
The first semiconductor memory device 91 has a chip select signal input xe2x80x9c/Sxe2x80x9d, an output enable signal input xe2x80x9c/OExe2x80x9d, a write enable signal input xe2x80x9c/Wxe2x80x9d, address inputs xe2x80x9cA0xcx9cAmxe2x80x9d, and data I/O ports xe2x80x9cDQ1xcx9cDQ16xe2x80x9d, as the interface ports for CPU 99. Data reading and writing at high speeds on the first semiconductor memory device 91 is performed using a memory bus between the first semiconductor memory device 91 and the CPU 99.
The second semiconductor memory device 92 has a chip select signal input xe2x80x9cCE#xe2x80x9d, an output enable signal input xe2x80x9cOE#xe2x80x9d, a write enable signal input xe2x80x9cWE#xe2x80x9d, a reset/power down signal input xe2x80x9cRP#xe2x80x9d, a write protect signal input xe2x80x9cWP#xe2x80x9d, address inputs xe2x80x9cA0xcx9cAnxe2x80x9d, and data I/O ports xe2x80x9cDQ0xcx9cDQ15xe2x80x9d, as the interface ports for the CPU 99. Data reading and writing on the second semiconductor memory device 92 is performed by transmitting commands from the address inputs or the data I/O ports.
The CPU 99 has as the interface ports for the memory devices 91 and 92 a chip select signal output xe2x80x9c/CSmxe2x80x9d which is connected via a control bus 96 to the xe2x80x9c/Sxe2x80x9d port of the first memory device 91, a chip select signal output xe2x80x9c/CSnxe2x80x9d which is connected via a control bus 93a to the xe2x80x9cCE#xe2x80x9d port of the second memory device 92, a read signal output xe2x80x9c/RDxe2x80x9d which is connected via a control bus 93b to the xe2x80x9c/OExe2x80x9d port of the first memory device 91 and the xe2x80x9cOE#xe2x80x9d port of the second memory device 92, a write signal output xe2x80x9c/WRxe2x80x9d which is connected via a control bus 93c to the xe2x80x9c/Wxe2x80x9d port of the first memory device 91 and the xe2x80x9cWE#xe2x80x9d port of the second memory device 92, an I/O port xe2x80x9cI/O Port1xe2x80x9d which is connected via a control bus 93d to the xe2x80x9cRP#xe2x80x9d port of the second memory device 92, an I/O port xe2x80x9cI/O Port2xe2x80x9d which is connected via a control bus 93e to the xe2x80x9cWP#xe2x80x9d port of the second memory device 92, address outputs xe2x80x9cMA0xcx9cMAxxe2x80x9d which are connected via an address bus 94 to the corresponding xe2x80x9cA0xcx9cAmxe2x80x9d of the first memory device 91 and the xe2x80x9cA0xcx9cAnxe2x80x9d of the second memory device 92, and data I/O ports xe2x80x9cD0xcx9cD15xe2x80x9d which are connected via an data bus 95 to the xe2x80x9cDQ1xcx9cDQ16xe2x80x9d ports of the first device 91 and the xe2x80x9cDQ0xcx9cDQ15xe2x80x9d of the second memory device 92.
The data read/write operation of the semiconductor memory system will now be explained. The CPU 99 selects either its xe2x80x9c/CSmxe2x80x9d or xe2x80x9c/CSnxe2x80x9d port for accessing the first memory device 91 or the second memory device 92. For accessing the first memory device 91, the CPU 99 turns its xe2x80x9c/CSmxe2x80x9d port to L level and selects one of the xe2x80x9cA0xcx9cAmxe2x80x9d port via the address bus 95. When the xe2x80x9c/RDxe2x80x9d port is turned to L level, the CPU 99 can read data from the first memory device 91. On the other hand, when selecting one of the xe2x80x9cDQ1xcx9cDQ16xe2x80x9d ports via the data bus 95 and turning the xe2x80x9c/WRxe2x80x9d port to L level, the CPU 99 can write data onto the first memory device 91.
For accessing the second memory device 92, the CPU 99 drives its two ports xe2x80x9cI/O Port 1xe2x80x9d and xe2x80x9cI/O Port 2xe2x80x9d port to turn both the xe2x80x9cRP#xe2x80x9d and xe2x80x9cWP#xe2x80x9d ports of the memory device 92 to H level. When the xe2x80x9c/CSnxe2x80x9d port is turned to L level, the second memory device 92 can be accessed. Then, the CPU 99 releases a read command to the data bus 95 and turns its xe2x80x9c/WRxe2x80x9d port to L level. At the succeeding cycle, when the xe2x80x9c/RDxe2x80x9d port is turned to L level with the address bus 94 enabled, the data reading from the second memory device 92 can be carried out. Similarly, the CPU 99 releases a program command to the data bus 95 and turns its xe2x80x9c/WRxe2x80x9d port to L level. At the succeeding cycle, when the xe2x80x9c/WRxe2x80x9d port is turned to L level with the address bus 94 and data bus 95 enabled, the data writing onto the second memory device 92 can be carried out.
It is however necessary in the conventional system to write data at two different cycles into the two semiconductor memory devices which are different from each other in the way for controlling the data read/write operation. As the data writing data into each semiconductor memory device is separately carried out, the overall processing operation will be elongated.
It is an object of the present invention to provide substantially a semiconductor memory system having a plurality of semiconductor memory devices of which the read and write operations can be controlled by commands received from an external CPU, which can minimize the length of time required for reading and writing data on two or more semiconductor memory devices thus increasing the efficiency of data processing.
A semiconductor memory system in one aspect of the present invention includes a first semiconductor memory device, a second semiconductor memory device and a controller.
The first semiconductor memory device has a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and is arranged so that data reading and writing at high speeds is performed through the interface of the buses connected to the address inputs and the data I/O ports. The second semiconductor memory device has a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and is arranged so that data reading and writing is controlled by commands provided via the data I/O ports. The controller is arranged responsive to commands from the CPU for controlling the read and write operation of each of the semiconductor memory devices.
In this aspect of the semiconductor memory system, a single write operation of the CPU to the controller can simultaneously write the same data into the semiconductor memory devices. Accordingly, the data writing of the semiconductor memory system can be improved in the efficiency as its consuming time is minimized.